ch7 review silberschatz operating systems concepts essentials 2nd ed
Review Questions
Section 7.1
7.1 What two registers can be used to provide a simple form of memory protection? Relocation register and Limit register
7.2 List the three different times at which address binding may occur. Compile time, Load time, Execution time
7.3 True or False? An address generated by the CPU is also referred to as a physical address. False. An address generated by the CPU is a logical or virtual address, an address in memory is a physical address
7.4 What is the hardware device that maps virtual to physical addresses? Memory Management Unit
Section 7.2
7.5 What is the backing store? Fast disk space. A process can be swapped out of memory into a backing store temporarily and then returned to memory for continued execution
7.6 True or False? Mobile systems typicallyuse swapping. False typically mobile systems do not support swapping
Section 7.3
7.7 What are the three strategies for selecting a free hole from the set of available holes? First-fit, Best-fit, Worst-fit
7.8 What are the two forms of fragmentation? External and internal
Section 7.4
7.9 List at least two possible parts of a program that may be assigned separate segments. Code, Global Variables, the heap, stacks, the standard c library
Section 7.5
7.10 What are the two parts of an address generated by the CPU? page number (p) and page offset (d)
7.11 What does each entry in the page table contain? the base address of each page in physical memory, a page number and frame number
7.12 True or False? Fragmentation can still occur in paging systems. True internal fragmentation can occur. external can not
Chapter 7 Main Memory
7.13 What is the term that describes when a page number is not present in the TLB? TLB miss. a memory reference to the page table is made and the page and frame number are added to the transition look-aside buffer
Section 7.6
7.14 If a page offset is 13 bits, how large (in bytes) is the page? 8192 bytes (8KB) or 10^13
7.15 How many entries are in a two-level page table with a 20-bit page number? 1,048,576 entries
7.16 What is an alternative to hierarchical paging for large(>32bits)address sizes? Hashed Page Table or Inverted Page Table
Section 7.7
7.17 True or False? IA-32 address translation involves both paging and segmentation. True
7.18 True or False? In practice, all 64 bits are used with IA-64 addressing. False, IA-64/x86-64 addressing uses a 48-bit address and supports page sizes of 4KB, 2MB, and 1GB using four levels of paging hierarchy.
Section 7.8
7.19 What are the three components of a 32-bit ARM address? outer page, inner page, and offset